The present invention relates to a digital serial programmable loop filter for use in high frequency control systems such as 125 MHz Fiber Distributed Data Interface (FDDI) Phase-Locked Loop (PLL) applications.
In control systems such as PLLs, 2nd order loops are widely used due to their good dynamic tracking performance. In general, the tracking characteristic is heavily influenced by the bandwidth and the damping factor of the loop. To optimize the loop performance, it is important to minimize the variations in these two parameters caused by component or process tolerances. As a consequence, a digital approach is preferred over an analog approach for constructing the loop filter because performance variations due to component/process tolerances can be eliminated.
Digital implementations of high frequency loop filters have, however, typically utilized multi-bit parallel processing which adds to circuit complexity and size and cost.
From the above it is seen that an improved loop filter is desired for high frequency control system applications.